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Exploring MRAM for On-Chip Texture Storage in Rendering Applications

  • Nicolas Villegas*
  • , Stefano Romanini
  • , Moritz Scherer
  • , Warren Hunt
  • , Syed Shakib Sarwar
  • , Barbara De Salvo
  • , Chiao Liu
  • , Francesco Conti
  • , Davide Rossi
  • , Luca Benini
  • , Jorge Gómez
  • *Autor correspondiente de este trabajo

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

Resumen

In recent years, Magnetoresistive Random-Access Memory (MRAM) has attracted considerable attention as a high-density, non-volatile alternative to conventional embedded memory technologies. While MRAM has been recently adopted for storing neural network weights, its application in rendering workloads remains unexplored. In this study, we investigate the potential of MRAM for on-chip texture storage within a tile-based rasterization workload. Leveraging Siracusa, a RISC-V-based System-on-Chip (SoC) that integrates both MRAM and SRAM at the same memory hierarchy level, we conduct a comparative evaluation focusing on latency and energy consumption across varying frame rates. The results suggest that MRAM achieves substantial energy savings at lower frame rates due to its ability to enter deep-sleep mode between rendering cycles. However, this benefit diminishes as frame rates increase, with SRAM becoming more energy-efficient beyond a threshold of 43 frames per second. These findings demonstrate that MRAM is particularly wellsuited to read-intensive, energy-constrained rendering tasks.

Idioma originalInglés
Título de la publicación alojada2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration, VLSI-SoC 2025
EditorialIEEE Computer Society
ISBN (versión digital)9798331598129
DOI
EstadoPublicada - 2025
Evento33rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2025 - Puerto Varas, Chile
Duración: 12 oct. 202515 oct. 2025

Serie de la publicación

NombreIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (versión impresa)2324-8432
ISSN (versión digital)2324-8440

Conferencia o congreso

Conferencia o congreso33rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2025
País/TerritorioChile
CiudadPuerto Varas
Período12/10/2515/10/25

Nota bibliográfica

Publisher Copyright:
© 2025 IEEE.

ODS de las Naciones Unidas

Este resultado contribuye a los siguientes Objetivos de Desarrollo Sostenible

  1. ODS 7: Energía asequible y no contaminante
    ODS 7: Energía asequible y no contaminante

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