A Topology-Independent and Scalable Methodology for Automated LDO Design Using Open PDKs

This work proposes a methodology for the automated sizing of transistors in analog integrated circuits, based on a modular and hierarchical representation of the circuit. The methodology combines structured design techniques and systematic design flow to generate a hierarchy of simplified macromodels that define their specifications locally and are interconnected with other macromodels or transistor-level primitive blocks. These primitive blocks can be described using symbolic models or pre-characterized data from look-up tables (LUTs). The symbolic representation of the system is obtained using Modified Nodal Analysis (MNA), and the exploration of each block is performed using local design spaces constrained by top-level specifications. The methodology is validated through the design of low dropout voltage regulators (LDOs) for DC-DC integrated power systems using open-source tools and three process design kits: Sky130A, GF180MCU, and IHP-SG13G2. Results show that the methodology allows the exploration of several topologies and technologies, demonstrating its versatility and modularity, which are key aspects in analog design.