Abstract
Low-latency and low-power edge AI is crucial for Augmented/Virtual Reality applications. Recent advances demonstrate that hybrid models, combining convolution layers (CNN) and transformers (ViT), often achieve a superior accuracy/performance tradeoff on various computer vision and machine learning (ML) tasks. However, hybrid ML models can present system challenges for latency and energy efficiency due to their diverse nature in dataflow and memory access patterns. In this work, we leverage architecture heterogeneity from Neural Processing Units (NPU) and Compute-In-Memory (CIM) and explore diverse execution schemas for efficient hybrid model executions. We introduce H4H-NAS, a two-stage Neural Architecture Search (NAS) framework to automate the design of hybrid CNN/ViT models for heterogeneous edge systems featuring both NPU and CIM. We propose a two-phase incremental supernet training in our NAS to resolve gradient conflicts between sampled subnets caused by different block types in a hybrid model search space. Our H4H-NAS approach is also powered by a performance estimator built with NPU performance results measured on real silicon, and CIM performance based on industry IPs. H4H-NAS searches hybrid CNN-ViT models with fine granularity and achieves significant (up to 1.34%) top-1 accuracy improvement on ImageNet-1k. Moreover, results from our algorithm/hardware co-design reveal up to 56.08% overall latency and 41.72% energy improvements by introducing heterogeneous computing over baseline solutions. Overall, our framework guides the design of hybrid network architectures and system architectures for NPU+CIM heterogeneous systems.
Original language | English |
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Title of host publication | ASP-DAC 2025 - 30th Asia and South Pacific Design Automation Conference, Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 1133-1141 |
Number of pages | 9 |
ISBN (Electronic) | 9798400706356 |
DOIs | |
State | Published - 4 Mar 2025 |
Externally published | Yes |
Event | 30th Asia and South Pacific Design Automation Conference, ASP-DAC 2025 - Tokyo, Japan Duration: 20 Jan 2025 → 23 Jan 2025 |
Publication series
Name | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC |
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ISSN (Print) | 2153-6961 |
ISSN (Electronic) | 2153-697X |
Conference
Conference | 30th Asia and South Pacific Design Automation Conference, ASP-DAC 2025 |
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Country/Territory | Japan |
City | Tokyo |
Period | 20/01/25 → 23/01/25 |
Bibliographical note
Publisher Copyright:© 2025 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.
Keywords
- algorithm-hardware co-design
- compute-inmemory
- edge AI inference
- neural architecture search
- neural processing unit