Exploring MRAM for On-Chip Texture Storage in Rendering Applications

Nicolas Villegas; Stefano Romanini; Moritz Scherer; Warren Hunt; Syed Shakib Sarwar; Barbara De Salvo; Chiao Liu; Francesco Conti; Davide Rossi; Luca Benini; Jorge Gómez

doi:10.1109/VLSI-SoC64688.2025.11421770

Exploring MRAM for On-Chip Texture Storage in Rendering Applications

Nicolas Villegas^*
, Stefano Romanini
, Moritz Scherer
, Warren Hunt
, Syed Shakib Sarwar
, Barbara De Salvo
, Chiao Liu
, Francesco Conti
, Davide Rossi
, Luca Benini
, Jorge Gómez

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In recent years, Magnetoresistive Random-Access Memory (MRAM) has attracted considerable attention as a high-density, non-volatile alternative to conventional embedded memory technologies. While MRAM has been recently adopted for storing neural network weights, its application in rendering workloads remains unexplored. In this study, we investigate the potential of MRAM for on-chip texture storage within a tile-based rasterization workload. Leveraging Siracusa, a RISC-V-based System-on-Chip (SoC) that integrates both MRAM and SRAM at the same memory hierarchy level, we conduct a comparative evaluation focusing on latency and energy consumption across varying frame rates. The results suggest that MRAM achieves substantial energy savings at lower frame rates due to its ability to enter deep-sleep mode between rendering cycles. However, this benefit diminishes as frame rates increase, with SRAM becoming more energy-efficient beyond a threshold of 43 frames per second. These findings demonstrate that MRAM is particularly wellsuited to read-intensive, energy-constrained rendering tasks.

Original language	English
Title of host publication	2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration, VLSI-SoC 2025
Publisher	IEEE Computer Society
ISBN (Electronic)	9798331598129
DOIs	https://doi.org/10.1109/VLSI-SoC64688.2025.11421770
State	Published - 2025
Event	33rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2025 - Puerto Varas, Chile Duration: 12 Oct 2025 → 15 Oct 2025

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Conferencia o congreso

Conferencia o congreso	33rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2025
Country/Territory	Chile
City	Puerto Varas
Period	12/10/25 → 15/10/25

Bibliographical note

Publisher Copyright:
© 2025 IEEE.

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Emerging Memories
High-density memories
MRAM
Non-Volatile memories
SAHbased BVH rasterization
Tile-based rendering

Access to Document

10.1109/VLSI-SoC64688.2025.11421770

Cite this

Villegas, N., Romanini, S., Scherer, M., Hunt, W., Sarwar, S. S., De Salvo, B., Liu, C., Conti, F., Rossi, D., Benini, L., & Gómez, J. (2025). Exploring MRAM for On-Chip Texture Storage in Rendering Applications. In 2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration, VLSI-SoC 2025 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC64688.2025.11421770

@inproceedings{8a278dae4741460cb839ce59b3aa8637,

title = "Exploring MRAM for On-Chip Texture Storage in Rendering Applications",

abstract = "In recent years, Magnetoresistive Random-Access Memory (MRAM) has attracted considerable attention as a high-density, non-volatile alternative to conventional embedded memory technologies. While MRAM has been recently adopted for storing neural network weights, its application in rendering workloads remains unexplored. In this study, we investigate the potential of MRAM for on-chip texture storage within a tile-based rasterization workload. Leveraging Siracusa, a RISC-V-based System-on-Chip (SoC) that integrates both MRAM and SRAM at the same memory hierarchy level, we conduct a comparative evaluation focusing on latency and energy consumption across varying frame rates. The results suggest that MRAM achieves substantial energy savings at lower frame rates due to its ability to enter deep-sleep mode between rendering cycles. However, this benefit diminishes as frame rates increase, with SRAM becoming more energy-efficient beyond a threshold of 43 frames per second. These findings demonstrate that MRAM is particularly wellsuited to read-intensive, energy-constrained rendering tasks.",

keywords = "Emerging Memories, High-density memories, MRAM, Non-Volatile memories, SAHbased BVH rasterization, Tile-based rendering",

author = "Nicolas Villegas and Stefano Romanini and Moritz Scherer and Warren Hunt and Sarwar, \{Syed Shakib\} and \{De Salvo\}, Barbara and Chiao Liu and Francesco Conti and Davide Rossi and Luca Benini and Jorge G{\'o}mez",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 33rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2025 ; Conference date: 12-10-2025 Through 15-10-2025",

year = "2025",

doi = "10.1109/VLSI-SoC64688.2025.11421770",

language = "English",

series = "IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC",

publisher = "IEEE Computer Society",

booktitle = "2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration, VLSI-SoC 2025",

address = "United States",

}

Villegas, N, Romanini, S, Scherer, M, Hunt, W, Sarwar, SS, De Salvo, B, Liu, C, Conti, F, Rossi, D, Benini, L & Gómez, J 2025, Exploring MRAM for On-Chip Texture Storage in Rendering Applications. in 2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration, VLSI-SoC 2025. IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, IEEE Computer Society, 33rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2025, Puerto Varas, Chile, 12/10/25. https://doi.org/10.1109/VLSI-SoC64688.2025.11421770

Exploring MRAM for On-Chip Texture Storage in Rendering Applications. / Villegas, Nicolas; Romanini, Stefano; Scherer, Moritz et al.
2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration, VLSI-SoC 2025. IEEE Computer Society, 2025. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Exploring MRAM for On-Chip Texture Storage in Rendering Applications

AU - Villegas, Nicolas

AU - Romanini, Stefano

AU - Scherer, Moritz

AU - Hunt, Warren

AU - Sarwar, Syed Shakib

AU - De Salvo, Barbara

AU - Liu, Chiao

AU - Conti, Francesco

AU - Rossi, Davide

AU - Benini, Luca

AU - Gómez, Jorge

PY - 2025

Y1 - 2025

N2 - In recent years, Magnetoresistive Random-Access Memory (MRAM) has attracted considerable attention as a high-density, non-volatile alternative to conventional embedded memory technologies. While MRAM has been recently adopted for storing neural network weights, its application in rendering workloads remains unexplored. In this study, we investigate the potential of MRAM for on-chip texture storage within a tile-based rasterization workload. Leveraging Siracusa, a RISC-V-based System-on-Chip (SoC) that integrates both MRAM and SRAM at the same memory hierarchy level, we conduct a comparative evaluation focusing on latency and energy consumption across varying frame rates. The results suggest that MRAM achieves substantial energy savings at lower frame rates due to its ability to enter deep-sleep mode between rendering cycles. However, this benefit diminishes as frame rates increase, with SRAM becoming more energy-efficient beyond a threshold of 43 frames per second. These findings demonstrate that MRAM is particularly wellsuited to read-intensive, energy-constrained rendering tasks.

AB - In recent years, Magnetoresistive Random-Access Memory (MRAM) has attracted considerable attention as a high-density, non-volatile alternative to conventional embedded memory technologies. While MRAM has been recently adopted for storing neural network weights, its application in rendering workloads remains unexplored. In this study, we investigate the potential of MRAM for on-chip texture storage within a tile-based rasterization workload. Leveraging Siracusa, a RISC-V-based System-on-Chip (SoC) that integrates both MRAM and SRAM at the same memory hierarchy level, we conduct a comparative evaluation focusing on latency and energy consumption across varying frame rates. The results suggest that MRAM achieves substantial energy savings at lower frame rates due to its ability to enter deep-sleep mode between rendering cycles. However, this benefit diminishes as frame rates increase, with SRAM becoming more energy-efficient beyond a threshold of 43 frames per second. These findings demonstrate that MRAM is particularly wellsuited to read-intensive, energy-constrained rendering tasks.

KW - Emerging Memories

KW - High-density memories

KW - MRAM

KW - Non-Volatile memories

KW - SAHbased BVH rasterization

KW - Tile-based rendering

UR - https://www.scopus.com/pages/publications/105035329170

U2 - 10.1109/VLSI-SoC64688.2025.11421770

DO - 10.1109/VLSI-SoC64688.2025.11421770

M3 - Conference contribution

AN - SCOPUS:105035329170

T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

BT - 2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration, VLSI-SoC 2025

PB - IEEE Computer Society

T2 - 33rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2025

Y2 - 12 October 2025 through 15 October 2025

ER -

Villegas N, Romanini S, Scherer M, Hunt W, Sarwar SS, De Salvo B et al. Exploring MRAM for On-Chip Texture Storage in Rendering Applications. In 2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration, VLSI-SoC 2025. IEEE Computer Society. 2025. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). doi: 10.1109/VLSI-SoC64688.2025.11421770

Exploring MRAM for On-Chip Texture Storage in Rendering Applications

Abstract

Publication series

Conferencia o congreso

Bibliographical note

UN SDGs

Keywords

Access to Document

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Cite this