TY - JOUR
T1 - BEOL-Compatible Superlattice FEFET Analog Synapse with Improved Linearity and Symmetry of Weight Update
AU - Aabrar, Khandker Akif
AU - Kirtania, Sharadindu Gopal
AU - Liang, Fu Xiang
AU - Gomez, Jorge
AU - Jose, Matthew San
AU - Luo, Yandong
AU - Ye, Huacheng
AU - Dutta, Sourav
AU - Ravikumar, Priyankka G.
AU - Ravindran, Prasanna Venkatesan
AU - Khan, Asif Islam
AU - Yu, Shimeng
AU - Datta, Suman
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2022/4/1
Y1 - 2022/4/1
N2 - Pseudo-crossbar arrays using ferroelectric field effect transistor (FEFET) mitigates weight movement and allows in situ vector-matrix multiplication (VMM), which can significantly accelerate online training of deep neural networks (DNNs). However, the training accuracy of DNNs using conventional FEFETs is low because of the non-idealities, such as nonlinearity, asymmetry, limited bit precision, and limited dynamic range of the weight updates. The limited endurance of these devices degrades the training accuracy further. Here, we show a novel approach for designing the gate-stack of an FEFET analog synapse using a superlattice (SL) of ferroelectric (FE)/dielectric (DE)/FE. The partial polarization states are stabilized by harnessing the depolarization field from the DE spacer, which mitigates the weight update non-idealities. We demonstrate a 7-bit SL-FEFET analog synapse with improved weight update profile, resulting in 94.1% online training accuracy for MNIST handwritten digit classification task. The device uses an indium-tungsten-oxide (IWO) channel and back-end-of line (BEOL)-compatible process flow. The absence of low-k interlayer (IL) results in high endurance (>1010 cycles), while the BEOL compatibility paves the way to high-density integration of pseudo-crossbar arrays and flexibility for neuromorphic circuit design.
AB - Pseudo-crossbar arrays using ferroelectric field effect transistor (FEFET) mitigates weight movement and allows in situ vector-matrix multiplication (VMM), which can significantly accelerate online training of deep neural networks (DNNs). However, the training accuracy of DNNs using conventional FEFETs is low because of the non-idealities, such as nonlinearity, asymmetry, limited bit precision, and limited dynamic range of the weight updates. The limited endurance of these devices degrades the training accuracy further. Here, we show a novel approach for designing the gate-stack of an FEFET analog synapse using a superlattice (SL) of ferroelectric (FE)/dielectric (DE)/FE. The partial polarization states are stabilized by harnessing the depolarization field from the DE spacer, which mitigates the weight update non-idealities. We demonstrate a 7-bit SL-FEFET analog synapse with improved weight update profile, resulting in 94.1% online training accuracy for MNIST handwritten digit classification task. The device uses an indium-tungsten-oxide (IWO) channel and back-end-of line (BEOL)-compatible process flow. The absence of low-k interlayer (IL) results in high endurance (>1010 cycles), while the BEOL compatibility paves the way to high-density integration of pseudo-crossbar arrays and flexibility for neuromorphic circuit design.
KW - Analog synapse
KW - backend-of-the-line (BEOL)
KW - ferroelectric field effect transistor (FEFET)
KW - superlattice (SL)
UR - http://www.scopus.com/inward/record.url?scp=85123698368&partnerID=8YFLogxK
U2 - 10.1109/TED.2022.3142239
DO - 10.1109/TED.2022.3142239
M3 - Article
AN - SCOPUS:85123698368
SN - 0018-9383
VL - 69
SP - 2094
EP - 2100
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 4
ER -