TY - JOUR
T1 - A robust phase-locked loop algorithm to synchronize static-power converters with polluted AC systems
AU - Perez, Marcelo A.
AU - Espinoza, José R.
AU - Moran, Luis A.
AU - Torres, Miguel A.
AU - Araya, Ernesto A.
PY - 2008/5
Y1 - 2008/5
N2 - In this paper, a phase-locked loop algorithm appropriated for digital-signal-processor-based control implementations, where the operation of a static-power converter needs to be synchronized with an ac network, is presented. The proposed algorithm includes a multiplier, a filter, a feedback closed loop, and a numerically controlled oscillator stage. As a result, a discrete sine (and cosine) signal is generated in synchronism with the fundamental component of an external-reference (ER) signal. Moreover, the sampling period of the algorithm is adjusted at each sampling instant such that an integer number of sampling periods per period of the ER signal is ensured. This is the main feature, and it is achieved by using a discrete rectangular window filter and a discrete controller. The proposed algorithm code is simple, stable, and presents high noise rejection. A comprehensive theoretical justification and various rigorous experimental tests are included.
AB - In this paper, a phase-locked loop algorithm appropriated for digital-signal-processor-based control implementations, where the operation of a static-power converter needs to be synchronized with an ac network, is presented. The proposed algorithm includes a multiplier, a filter, a feedback closed loop, and a numerically controlled oscillator stage. As a result, a discrete sine (and cosine) signal is generated in synchronism with the fundamental component of an external-reference (ER) signal. Moreover, the sampling period of the algorithm is adjusted at each sampling instant such that an integer number of sampling periods per period of the ER signal is ensured. This is the main feature, and it is achieved by using a discrete rectangular window filter and a discrete controller. The proposed algorithm code is simple, stable, and presents high noise rejection. A comprehensive theoretical justification and various rigorous experimental tests are included.
KW - Discrete-time systems
KW - Phase-locked loops
KW - Pulsewidth-modulated power converters
UR - http://www.scopus.com/inward/record.url?scp=44349189350&partnerID=8YFLogxK
U2 - 10.1109/TIE.2008.918638
DO - 10.1109/TIE.2008.918638
M3 - Article
AN - SCOPUS:44349189350
SN - 0278-0046
VL - 55
SP - 2185
EP - 2192
JO - IEEE Transactions on Industrial Electronics
JF - IEEE Transactions on Industrial Electronics
IS - 5
ER -